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Searching titles and descriptions for “CAD Engineer - Timing for Gate-Level Flows & Methodologies”. A match may be a passing mention rather than the job itself. Titles only.
36 roles across 63 listings · show every listing · page 2 of 2
4moGate-level SigEM/SEB/FIT CAD Engineer…in time (FIT), self-heating effect (SHE), and thermal analysis to develop, define, and refine the methodologies and flows for gate-level as well…
- 4moCellular ASIC Design Engineer
…DESIGN FLOW & METHODOLOGY DEVELOPMENT: - Establish design guidelines, methodologies, and standards for synthesis, place-and-route, timing closure, and signoff processes - Develop and optimize EDA…
- 4moCAD Gate-level 3DIC EM/IR Engineer
…We will apply your hands-on experience in power EM/IR analysis to develop, define and refine the methodologies and flows for gate-level…
- 4moGPU Top Level Physical Design Engineer
…with Floorplanning tools, P&R flows (Cadence or Synopsys) Experience with hierarchical design approach, top-down design, budgeting, timing and physical convergence. Experience integrating…
4moNPU/AI Processor Synthesis Lead…gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows…
- 7moSoC Physical Design Engineer, Top Level
…From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows is required. Familiar with…
- 7moNPU/AI Processor Synthesis Sr Staff Engineer
…gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows…
- 9moSynthesis Engineer, Lead/Staff/Sr Staff
…Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance…
- 11moNPU/AI Processor Synthesis Staff/ Sr Staff/ Technical Lead
…gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows…
- 12moExperienced GPU Top Level Physical Design Engineer
…for Yield and Manufacturability, multi Vt strategies and thermal Mgt. From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing…
- 1.4yNPU/AI Processor Synthesis - Principal Engineer/Manager
…gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows…