…We are seeking an ASIC Chip Manager to help drive development of future SoC processors to be used in client, workstation, embedded, and automotive…

…in Electrical Engineering, Computer Engineering, or Computer Science 5+ years of experience in ASIC RTL design Solid foundation in computer architecture and digital logic…

…We’re looking for a Senior Manager, Physical Design Engineering to build and lead a world-class Physical Design team delivering multi-billion-transistor…

…We are looking for a Senior Design Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate…

…in ASIC design verification 5+ years managing design verification engineers, including hiring and performance management, with experience leading senior and principal-level engineers Track…

…technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Physical Design Engineer to join the team. Responsibilities…

…We are looking for a Senior Design Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. Microsoft’s…

…About the role SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration…

…As a Physical Design Engineer, you will be responsible for Physical Design tasks at block, subsystem, sub-chip, and/or full-chip level. The…

…quantized paths — implemented against novel architectural features (matrix engines, on-chip reduction fabrics, software-managed memory hierarchies) and tuned until the remaining gap to…

…hiring of a few senior and principal level Physical Design engineers to work on Microsoft Next-Gen AI SOC chip. If hired, you will…

…quantized paths — implemented against novel architectural features (matrix engines, on-chip reduction fabrics, software-managed memory hierarchies) and tuned until the remaining gap to…

…We are looking for a Senior ASIC Design Engineer to join our Chip Design team and take ownership of Power Management IP — from micro…

…Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back…

…Successfully implementing and managing projects to meet ambitious deadlines and performance targets. What we need to see: BSc or MSc in Electrical Engineering or…

…all engineering issues within and across subsystems and chipset components. Ability to clearly communicate the engineering status of the project to senior management is…

…all engineering issues within and across subsystems and chipset components. Ability to clearly communicate the engineering status of the project to senior management is…

…chip (SoC) cycles. Experience in high-performance, high-frequency, and low-power designs. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer…

…ASICs. In this role, you will execute package layout tasks from floor planning through tape out and manufacturing release, working closely with senior engineers…

…Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that…

…NPI cadence — build matrix, engineering reviews, DFx, issue triage, exit criteria — and keep it lightweight enough that a small, senior team actually uses it…

…Experience with AI accelerator systems (GPU, TPU, or other custom ASIC platforms) and their scale-up / scale-out fabrics. Familiarity with the chip-package…

…chips are at the heart of our Trainium machine learning instances, and we invite you to build them with us! As a senior SDE…

…Key job responsibilities - Lead and grow a team of SOC integration engineers responsible for critical deliverables in our ML accelerator chips - Drive technical decisions…

…To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world…