Jobs

Indexed directly from employers. Every age is their own publish date.

Jobs

Indexed directly from employers. Every age is their own publish date.

fable12 is not a job board. It is a record of how long each listing has actually been open, read straight from employers’ own hiring systems. Listings link to the employer; ages are the employer’s own publish date — how we know.

Not affiliated with any company listed. Boards last swept 23 Aug, 11:21 UTC.

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Jobs

Indexed directly from employers. Every age is their own publish date.

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Under a week4 1–4 weeks16 1–2 months26 2–12 months47 Over a year4

1,163 postings mention “ASIC Design Verification Engineer” in the description

97 roles · group by role · page 2 of 4

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11d
ASICS Design Verification Engineer-Senior
QualcommASICS EngineeringSan Diego, CA
Apply ASICS Design Verification Engineer-Senior at Qualcomm — opens Qualcomm’s own board
19d
Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
NVIDIAEngineer, VerificationSanta Clara, CA; Austin, TX; Westford, MA; Durham, NC; CARemote
Apply Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU at NVIDIA — opens NVIDIA’s own board
29d
ASIC Engineer, Power Management Design Verification
MetaInfrastructureSunnyvale, CA; Austin, TX
Apply ASIC Engineer, Power Management Design Verification at Meta — opens Meta’s own board
29d
ASIC Engineer, Design Verification
MetaInfrastructureSunnyvale, CA; Austin, TX
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
45d
Senior ASIC Verification Engineer - Networking Chip Design
NVIDIAEngineer, ASICShanghai, Shanghai
Apply Senior ASIC Verification Engineer - Networking Chip Design at NVIDIA — opens NVIDIA’s own board
51d
ASIC Engineer, Design Verification
MetaInfrastructureSunnyvale, CA; Austin, TX
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
52d
ASIC Engineer, Design Verification
MetaInfrastructureBangalore, India
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
52d
ASIC Engineer, Design Verification
MetaDesign & User ExperienceBangalore, India
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
52d
ASIC Engineer, Design Verification
MetaInfrastructureSunnyvale, CA; Austin, TX
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
59d
ASIC Engineer, Design Verification
MetaInfrastructureSunnyvale, CA; Austin, TX
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
4mo
ASICS Design Verification Engineer
QualcommASICS EngineeringSan Diego, CA
Apply ASICS Design Verification Engineer at Qualcomm — opens Qualcomm’s own board
6d
Design Verification Engineer — Memory Subsystem
QualcommASICS EngineeringSanta Clara, CA
Apply Design Verification Engineer — Memory Subsystem at Qualcomm — opens Qualcomm’s own board
9d
Chip Design Verification Engineer
NVIDIAEngineer, ASICTel Aviv-Yafo, Tel Aviv District
Apply Chip Design Verification Engineer at NVIDIA — opens NVIDIA’s own board
11d
Design Verification Engineer — Memory Subsystem
QualcommASICS EngineeringVancouver, BC; Markham, ON
Apply Design Verification Engineer — Memory Subsystem at Qualcomm — opens Qualcomm’s own board
13d
GSoC Design Verification Engineer
QualcommASICS EngineeringSan Diego, CA
Apply GSoC Design Verification Engineer at Qualcomm — opens Qualcomm’s own board
14d
Senior Chip Design Dynamic Verification Engineer
NVIDIAEngineer, ASICTel Aviv-Yafo, Tel Aviv District
Apply Senior Chip Design Dynamic Verification Engineer at NVIDIA — opens NVIDIA’s own board
19d
Mixed Signal Design Verification Engineer
QualcommASICS EngineeringSan Diego, CA
Apply Mixed Signal Design Verification Engineer at Qualcomm — opens Qualcomm’s own board
20d
Senior Design Verification Engineer - Interconnect IP
NVIDIAEngineer, ASICShanghai, Shanghai
Apply Senior Design Verification Engineer - Interconnect IP at NVIDIA — opens NVIDIA’s own board
27d
Senior Chip Design and Verification Engineer
NVIDIAEngineer, ASICTel Aviv-Yafo, Tel Aviv District
Apply Senior Chip Design and Verification Engineer at NVIDIA — opens NVIDIA’s own board
38d
SOC Design Verification Engineer– Pre-Si/Post-Si Verification
QualcommASICS EngineeringTijuana, B.C.
Apply SOC Design Verification Engineer– Pre-Si/Post-Si Verification at Qualcomm — opens Qualcomm’s own board
39d
Senior Chip Design Verification Engineer
NVIDIAEngineer, ASICב"ש, South District
Apply Senior Chip Design Verification Engineer at NVIDIA — opens NVIDIA’s own board
39d
SOC Design Verification Engineer-Staff
QualcommASICS EngineeringSan Diego, CA
Apply SOC Design Verification Engineer-Staff at Qualcomm — opens Qualcomm’s own board
39d
SOC Design Verification Engineer
QualcommASICS EngineeringSan Diego, CA
Apply SOC Design Verification Engineer at Qualcomm — opens Qualcomm’s own board
39d
SOC Design Verification Engineer, Staff– Pre-Si/Post-Si Verification
QualcommASICS EngineeringTijuana, B.C.
Apply SOC Design Verification Engineer, Staff– Pre-Si/Post-Si Verification at Qualcomm — opens Qualcomm’s own board
39d
SOC Design Verification Engineer– Pre-Si/Post-Si Verification
QualcommASICS EngineeringTijuana, B.C.
Apply SOC Design Verification Engineer– Pre-Si/Post-Si Verification at Qualcomm — opens Qualcomm’s own board

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Search jobs

Company

▾

Job function

▾

Level

▾

Country

▾

Workplace

▾

Age

▾

Under a week4 1–4 weeks16 1–2 months26 2–12 months47 Over a year4

1,163 postings mention “ASIC Design Verification Engineer” in the description

97 roles · group by role · page 2 of 4

Sort

11d
ASICS Design Verification Engineer-Senior
QualcommASICS EngineeringSan Diego, CA
Apply ASICS Design Verification Engineer-Senior at Qualcomm — opens Qualcomm’s own board
19d
Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
NVIDIAEngineer, VerificationSanta Clara, CA; Austin, TX; Westford, MA; Durham, NC; CARemote
Apply Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU at NVIDIA — opens NVIDIA’s own board
29d
ASIC Engineer, Power Management Design Verification
MetaInfrastructureSunnyvale, CA; Austin, TX
Apply ASIC Engineer, Power Management Design Verification at Meta — opens Meta’s own board
29d
ASIC Engineer, Design Verification
MetaInfrastructureSunnyvale, CA; Austin, TX
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
45d
Senior ASIC Verification Engineer - Networking Chip Design
NVIDIAEngineer, ASICShanghai, Shanghai
Apply Senior ASIC Verification Engineer - Networking Chip Design at NVIDIA — opens NVIDIA’s own board
51d
ASIC Engineer, Design Verification
MetaInfrastructureSunnyvale, CA; Austin, TX
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
52d
ASIC Engineer, Design Verification
MetaInfrastructureBangalore, India
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
52d
ASIC Engineer, Design Verification
MetaDesign & User ExperienceBangalore, India
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
52d
ASIC Engineer, Design Verification
MetaInfrastructureSunnyvale, CA; Austin, TX
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
59d
ASIC Engineer, Design Verification
MetaInfrastructureSunnyvale, CA; Austin, TX
Apply ASIC Engineer, Design Verification at Meta — opens Meta’s own board
4mo
ASICS Design Verification Engineer
QualcommASICS EngineeringSan Diego, CA
Apply ASICS Design Verification Engineer at Qualcomm — opens Qualcomm’s own board
6d
Design Verification Engineer — Memory Subsystem
QualcommASICS EngineeringSanta Clara, CA
Apply Design Verification Engineer — Memory Subsystem at Qualcomm — opens Qualcomm’s own board
9d
Chip Design Verification Engineer
NVIDIAEngineer, ASICTel Aviv-Yafo, Tel Aviv District
Apply Chip Design Verification Engineer at NVIDIA — opens NVIDIA’s own board
11d
Design Verification Engineer — Memory Subsystem
QualcommASICS EngineeringVancouver, BC; Markham, ON
Apply Design Verification Engineer — Memory Subsystem at Qualcomm — opens Qualcomm’s own board
13d
GSoC Design Verification Engineer
QualcommASICS EngineeringSan Diego, CA
Apply GSoC Design Verification Engineer at Qualcomm — opens Qualcomm’s own board
14d
Senior Chip Design Dynamic Verification Engineer
NVIDIAEngineer, ASICTel Aviv-Yafo, Tel Aviv District
Apply Senior Chip Design Dynamic Verification Engineer at NVIDIA — opens NVIDIA’s own board
19d
Mixed Signal Design Verification Engineer
QualcommASICS EngineeringSan Diego, CA
Apply Mixed Signal Design Verification Engineer at Qualcomm — opens Qualcomm’s own board
20d
Senior Design Verification Engineer - Interconnect IP
NVIDIAEngineer, ASICShanghai, Shanghai
Apply Senior Design Verification Engineer - Interconnect IP at NVIDIA — opens NVIDIA’s own board
27d
Senior Chip Design and Verification Engineer
NVIDIAEngineer, ASICTel Aviv-Yafo, Tel Aviv District
Apply Senior Chip Design and Verification Engineer at NVIDIA — opens NVIDIA’s own board
38d
SOC Design Verification Engineer– Pre-Si/Post-Si Verification
QualcommASICS EngineeringTijuana, B.C.
Apply SOC Design Verification Engineer– Pre-Si/Post-Si Verification at Qualcomm — opens Qualcomm’s own board
39d
Senior Chip Design Verification Engineer
NVIDIAEngineer, ASICב"ש, South District
Apply Senior Chip Design Verification Engineer at NVIDIA — opens NVIDIA’s own board
39d
SOC Design Verification Engineer-Staff
QualcommASICS EngineeringSan Diego, CA
Apply SOC Design Verification Engineer-Staff at Qualcomm — opens Qualcomm’s own board
39d
SOC Design Verification Engineer
QualcommASICS EngineeringSan Diego, CA
Apply SOC Design Verification Engineer at Qualcomm — opens Qualcomm’s own board
39d
SOC Design Verification Engineer, Staff– Pre-Si/Post-Si Verification
QualcommASICS EngineeringTijuana, B.C.
Apply SOC Design Verification Engineer, Staff– Pre-Si/Post-Si Verification at Qualcomm — opens Qualcomm’s own board
39d
SOC Design Verification Engineer– Pre-Si/Post-Si Verification
QualcommASICS EngineeringTijuana, B.C.
Apply SOC Design Verification Engineer– Pre-Si/Post-Si Verification at Qualcomm — opens Qualcomm’s own board

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