…for first time right silicon. As a member of our STA CAD team, you will: • Develop, maintain, and enhance existing gate-level STA flows…

…About the Role As a Senior Physical Design Engineer, you will take ownership of block-level and subsystem-level physical implementation, driving timing closure…

…Mentoring junior engineers in different areas of timing flows and methodologies Understanding of Spice simulations: Hspice , FineSim , Monte Carlo analysis. Preferred Experience Driving timing…

…gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows…

…models in industry applications Experience in EDA Tool, CAD flow or TFM (Tool Flow Methodology) Proficiency with UNIX shell environment, Python, and code revision…

…Audit vendor PD flows and methodologies for any holes and set up issues. Suggest improvements to their methodology to optimize it to obtain the…

…models in industry applications Experience in EDA Tool, CAD flow or TFM (Tool Flow Methodology) Proficiency with UNIX shell environment, Python, and code revision…

…Design for Yield and Manufacturability and multi-vt strategies. From a CAD perspective, experience with floorplanning tools, P&R flows, global timing verification, and…

…in time (FIT), self-heating effect (SHE), and thermal analysis to develop, define, and refine the methodologies and flows for gate-level as well…

…DESIGN FLOW & METHODOLOGY DEVELOPMENT: - Establish design guidelines, methodologies, and standards for synthesis, place-and-route, timing closure, and signoff processes - Develop and optimize EDA…

…We will apply your hands-on experience in power EM/IR analysis to develop, define and refine the methodologies and flows for gate-level…

…with Floorplanning tools, P&R flows (Cadence or Synopsys) Experience with hierarchical design approach, top-down design, budgeting, timing and physical convergence. Experience integrating…

…gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows…

…From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows is required. Familiar with…

…gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows…

…Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance…

…gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows…

…for Yield and Manufacturability, multi Vt strategies and thermal Mgt. From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing…