…We are seeking an ASIC Chip Manager to help drive development of future SoC processors to be used in client, workstation, embedded, and automotive…

…quantized paths — implemented against novel architectural features (matrix engines, on-chip reduction fabrics, software-managed memory hierarchies) and tuned until the remaining gap to…

…hiring of a few senior and principal level Physical Design engineers to work on Microsoft Next-Gen AI SOC chip. If hired, you will…

…We are looking for a Senior ASIC Design Engineer to join our Chip Design team and take ownership of Power Management IP — from micro…

…Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back…

…Successfully implementing and managing projects to meet ambitious deadlines and performance targets. What we need to see: BSc or MSc in Electrical Engineering or…

…all engineering issues within and across subsystems and chipset components. Ability to clearly communicate the engineering status of the project to senior management is…

…chip (SoC) cycles. Experience in high-performance, high-frequency, and low-power designs. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer…

…ASICs. In this role, you will execute package layout tasks from floor planning through tape out and manufacturing release, working closely with senior engineers…

…Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that…

…NPI cadence — build matrix, engineering reviews, DFx, issue triage, exit criteria — and keep it lightweight enough that a small, senior team actually uses it…

…Experience with AI accelerator systems (GPU, TPU, or other custom ASIC platforms) and their scale-up / scale-out fabrics. Familiarity with the chip-package…

…chips are at the heart of our Trainium machine learning instances, and we invite you to build them with us! As a senior SDE…

…Key job responsibilities - Lead and grow a team of SOC integration engineers responsible for critical deliverables in our ML accelerator chips - Drive technical decisions…

…To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world…

…Experience managing highly complex hardware product portfolios involving deep tech or “first-of-a-kind” technology (e.g., quantum systems, ASICs, FPGA, advanced chip…

…Partner with test developers to harden the Test Engineer Datapath, preventing data tampering or leakage. Implement security baselines, endpoint protection, and AD Privilege Management…

…Engineering Group, Engineering Group > ASICS Engineering General Summary: We are seeking a senior-level Low Power MSIC-Analog System Technologist with deep expertise in…

…Self-motivated and self-managing. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation…

…Self-motivated and self-managing. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation…

…Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI, SW development, and Operations teams to productize new methodologies…

We are now looking for a Senior Architect (NVLink)! NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols…

…We're looking for a Senior Memory Systems Engineer to own HBM and LPDDR integration in sophisticated SoCs. This role covers the full stack…

…ability to present methodology decisions, risk assessments, and tape out readiness to senior management Principal Duties & Responsibilities: Leverages advanced ASIC knowledge and experience to…

…Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next…