Jobs
Indexed directly from employers. Every age is their own publish date.
Workplace
Age
Searching titles and descriptions for “CAD Engineer - Timing for Gate-Level Flows & Methodologies”. A match may be a passing mention rather than the job itself. Titles only.
10 roles across 14 listings · show every listing
- 9dNVIDIA 2027 Internships: Hardware ASIC Design
…and Measurement CAD and Physical Design Methodologies (Flow and Tools Development), Chop Floorplan, Power/Clock Distribution, Packaging, P&R and Timing Closure Performance, Verification…
12dAnalog/Mixed-Signal IP Engineering Program Manager…flows, and methodologies in an SoC environment. You will serve as the connective tissue across SoC Integration, IC Design, SoC PD, SoC DV, CAD…
19dTechnical Program Manager , Silicon OperationsAmazonProject/Program/Product Management--TechnicalSunnyvale, California; Bellevue, Washington; San Diego, California…Amazon Leo team is looking for a Business Operations Manager to support business and engineering stakeholders in selecting, developing and managing business relationships with…
22dPhysical Design Lead, ASICGoogleSunnyvale, CA, USA…Experience in structured placement methodologies (e.g., relative placement, data-flow driven layout, and customized power-grid stitching for dense blocks). Experience with tools…
22dSenior Silicon Engineer…Own block-level DFT architecture, specifications, and implementation for logic and memory test solutions. Drive DFT timing closure and signoff across Scan, MBIST, LBIST…
- 24dPhysical Design Engineer, Synthesis and Implementation
…Own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions. Optimize synthesis strategies, constraints, and flows to meet performance…
24dSenior Timing Engineer - Cork, Ireland…Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for…
- 25dDisplay Synthesis, Senior
…Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance…
- 25dSoC Physical Design Engineer, PnR
…distribution, timing closure, physical and electrical verification Experience with physical design construction and analysis flows and methodology MS in Electrical/Electronics/Computer Engineering or…
- 26dImplementation Engineer, Staff
…Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance…