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Searching titles and descriptions for “Verification Engineer, Memory Subsystem”. A match may be a passing mention rather than the job itself. Titles only.
6 roles
- 1.2ySenior Verification Engineer, Memory Subsystem
…Responsible for performance and deadlock verification of the GPU memory subsystem unit. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven…
1yASIC Architect…architectural specifications and interface definitions for compute blocks and subsystems - Collaborate with RTL, verification, physical design, and software teams to ensure architectural feasibility and…
- 1.2yDesign Verification Engineer - Internal IP
…Key responsibilities - Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems). - Define and execute verification plans covering…
- 1.2ySenior ASIC Design Engineer - NOC IP
…senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in…
- 1.2ySenior IP DV Engineer - NOC IP
NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the…
2yCPU Microarchitect/RTL Engineer…verification * Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance * Design delivery - work with multifunctional engineering…