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Searching titles and descriptions for “Compiler Engineer, Graph Compiler Performance Optimization”. A match may be a passing mention rather than the job itself. Titles only.
9 roles across 12 listings · show every listing
1yCAD and PPA Methodology Engineer…Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a member of the Graphics team, the successful applicant will help develop new flows…
- 1.1ySenior Math Libraries Engineer - Sparsity in AI
…equivalent technologies Experience with domain-specific language design and compiler optimizations, in particular sparse compilers (MLIR or TACO) Excellent C++, Python, and CUDA programming…
1.1yFull Stack LLM Engineer…model architecture translation, graph lowering, compiler optimizations, runtime integration, and performance tuning. - Debug performance and correctness issues spanning model code, compiler IRs, runtime behavior…
- 1.2yGPU Power Systems Engineer
…Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: Analyze and evaluate GPU architecture/microarchitecture and workload for performance and power optimizations GPU power…
1.3yMember of Technical Staff, Performance Optimization…Electrical Engineering, or a related field - Experience optimizing large models for training and inference (LLMs, VLMs, or video models) - Knowledge of compiler stacks or…
- 1.3ySenior SRAM Circuit Design Engineer
…One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners…
1.4ySoftware Engineer Rendering - Netflix Animation Studios…Practice in writing high performance code, vectorized code, with a good understanding of parallel programming, compilers and optimization. Familiarity with DCC applications such as…
1.4yLLM Inference Frameworks and Optimization EngineerTogether AIResearchSan Francisco, Singapore, Amsterdamhalf of Together AI’s roles are under 3 months…Knowledge of inference optimization, such as workload scheduling, CUDA graph, compiled, efficient kernels Soft Skills: Strong analytical problem-solving skills with a performance-driven…
3.2yDigital IC Design EngineerNeuralinkEngineering DepartmentAustin, Texas, United States; South San Francisco, California, United Stateshalf of Neuralink’s roles are under 6 months…Design and optimization of hardware/software interface with firmware engineers Application-specific architecture optimization including: Complex system modeling for energy and performance benchmarks Workload…