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Indexed directly from employers. Every age is their own publish date.
Searching titles and descriptions for “CAD Engineer - Timing for Gate-Level Flows & Methodologies”. A match may be a passing mention rather than the job itself. Titles only.
1 role
1.4yNPU/AI Processor Synthesis - Principal Engineer/Manager…gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus). Develop and maintain synthesis scripts and flows…