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Searching titles and descriptions for “CAD Engineer – Design Verification Methodology”. A match may be a passing mention rather than the job itself. Titles only.
12 roles across 15 listings · show every listing
1yCAD and PPA Methodology Engineer…design and ASIC design flow from RTL to GDS such as synthesis, static timing analysis, formal verification, physical design, ECO generation and verification. They…
1yPhysical Design Engineer…etc.) - Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and…
1.1yCPU Design Timing Engineer…methodology including but not limited to physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification…
- 1.1yCPU Full Chip Physical Integration Engineer
…As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development…
- 1.1yPhysical Design Engineer (Engineer up to Principal Level)QualcommASICS EngineeringSan Diego, CA; Austin, TX; Santa Clara, CAhalf of Qualcomm’s roles are under 3 months
…Drive cross-functional technical alignment among Design, DFT, CAD, Verification, and Product Engineering teams. Develop scalable methodologies, flow improvements, and automation solutions adopted across…
- 1.2ySr. Staff CPU Physical Design CAD EngineerQualcommCPU EngineeringSanta Clara, CA; Austin, TX; San Diego, CAhalf of Qualcomm’s roles are under 3 months
…As CPU Physical Design CAD engineer, you will build and support the world’s best implementation tools and flows. Your tools and flows will…
- 1.3ySenior ASIC Verification Engineer - GPU
NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world’s leading SoC's and GPU's. This…
- 1.3ySenior ICV CAD Engineer
…You would be responsible for supporting and maintaining CAD tools used by IC designers including Virtuoso, IC-Manage, DRC/LVS verification tools, extractions, and…
- 1.3ySenior VLSI CAD and AI Automation EngineerNVIDIAEngineer, ASICYokne'am Illit, North District; Tel Aviv-Yafo, Tel Aviv Districthalf of NVIDIA’s roles are under 3 months
…design process. Continuously review emerging AI technologies and methodologies to keep our CAD environment up-to-date. Provide technical support and training to engineering…
- 1.9ySenior VLSI Integration EngineerNVIDIAEngineer, ASICTel Aviv-Yafo, Tel Aviv District; Ra'anana, Center District; ב"ש, South District; Yokne'am Illit, North Districthalf of NVIDIA’s roles are under 3 months
…top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have…
- 1.9yIP Logic Design Engineer - Advanced Technologies Group
…RTL design into GDS, run various design verification flows and provide guidelines to other designers, and participate in establishing CAD and design methodologies for…
2.2yLow Observables Engineer, RCSAndurilAir Dominance & StrikeCosta Mesa, California, United Stateshalf of Anduril’s roles are under 2 months…Our Low Observables engineering team is responsible for designing, analyzing, testing, and sustaining stealth features that reduce radar (RCS) and infrared (IR) signatures , ensuring…