…applied research at the intersection of AI and ASIC design. Large language models, coding agents, and agentic AI are transforming how chips get designed…

…This role is designed for talented engineers passionate about learning through hands-on work with Python, Bash, Ansible, Linux, bare-metal servers, networking equipment…

…Work with user researchers, interaction designers, engineers, product managers and visual designers to craft the best possible design. Chip in positively to craft design…

…Engineering Group, Engineering Group > Systems Engineering General Summary: This individual independently plans, performs the moderately-defined responsibility for the research, design, development, verification, debugging…

…Helps verify that the RTL design meets the performance goals. Works with multi-functional engineering team to implement and validate physical design on the…

…engineering: managing the large scale distributed systems that orchestrate evals for our frontier models, building and scaling the harnesses researchers use to design and…

…Work closely with design, Customer engineering, product/test engineering and packaging engineering team to develop reliability qualification plan. Work closely with DFT team and…

…Bachelor’s degree in an engineering discipline 5+ years of research and/or industry experience in RF/microwave circuit design Experience with GaAs and…

…Bachelor’s degree in an engineering discipline 2+ years of research and/or industry experience in RF/microwave circuit design PREFERRED SKILLS AND EXPERIENCE…

…Bachelor’s degree in an engineering discipline 5+ years of research and/or industry experience in RF/microwave circuit design PREFERRED SKILLS AND EXPERIENCE…

…Experience with reading hardware description languages (SystemVerilog) and chip design flow, and building test automation tools and scripts. Passion for unusual computer architectures.

…Experience with multiple SoCs with silicon success and with chip design flow. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering…

…As a senior software engineer, you will craft highly efficient software to automate and facilitate chip design and verification processes. What You'll be…

…Engineering Group, Engineering Group > Systems Engineering General Summary: The XR Labs team at Qualcomm Bangalore designs systems that realize the prowess of XR devices…

…As an IC4 engineer, you will be expected to drive projects from design through launch, make sound technical tradeoffs, raise the quality bar through…

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and…

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and…

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and…

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and…

…As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture and also help…

…Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios…

…These tools give kernel developers, compiler and runtime teams, architects, and design verification engineers visibility into both correctness and performance. Your work will help…

…These may involve novel approaches not yet established in the industry Work across hardware and software, to solve co-design problems with other Research…

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and…

…We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first…